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3509 lines (3011 loc) · 119 KB
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/*
* Copyright (C) 2012 Apple Inc. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY APPLE INC. ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL APPLE INC. OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
* OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef ARM64Assembler_h
#define ARM64Assembler_h
#if ENABLE(ASSEMBLER) && CPU(ARM64)
#include "AssemblerBuffer.h"
#include <wtf/Assertions.h>
#include <wtf/Vector.h>
#include <stdint.h>
#define CHECK_DATASIZE_OF(datasize) ASSERT(datasize == 32 || datasize == 64)
#define DATASIZE_OF(datasize) ((datasize == 64) ? Datasize_64 : Datasize_32)
#define MEMOPSIZE_OF(datasize) ((datasize == 8 || datasize == 128) ? MemOpSize_8_or_128 : (datasize == 16) ? MemOpSize_16 : (datasize == 32) ? MemOpSize_32 : MemOpSize_64)
#define CHECK_DATASIZE() CHECK_DATASIZE_OF(datasize)
#define DATASIZE DATASIZE_OF(datasize)
#define MEMOPSIZE MEMOPSIZE_OF(datasize)
#define CHECK_FP_MEMOP_DATASIZE() ASSERT(datasize == 8 || datasize == 16 || datasize == 32 || datasize == 64 || datasize == 128)
namespace JSC {
ALWAYS_INLINE bool isInt9(int32_t value)
{
return value == ((value << 23) >> 23);
}
ALWAYS_INLINE bool isUInt5(int32_t value)
{
return !(value & ~0x1f);
}
ALWAYS_INLINE bool isUInt12(int32_t value)
{
return !(value & ~0xfff);
}
ALWAYS_INLINE bool isUInt12(intptr_t value)
{
return !(value & ~0xfffL);
}
class UInt5 {
public:
explicit UInt5(int value)
: m_value(value)
{
ASSERT(isUInt5(value));
}
operator int() { return m_value; }
private:
int m_value;
};
class UInt12 {
public:
explicit UInt12(int value)
: m_value(value)
{
ASSERT(isUInt12(value));
}
operator int() { return m_value; }
private:
int m_value;
};
class PostIndex {
public:
explicit PostIndex(int value)
: m_value(value)
{
ASSERT(isInt9(value));
}
operator int() { return m_value; }
private:
int m_value;
};
class PreIndex {
public:
explicit PreIndex(int value)
: m_value(value)
{
ASSERT(isInt9(value));
}
operator int() { return m_value; }
private:
int m_value;
};
class LogicalImmediate {
public:
static LogicalImmediate create32(uint32_t value)
{
// Check for 0, -1 - these cannot be encoded.
if (!value || !~value)
return InvalidLogicalImmediate;
// First look for a 32-bit pattern, then for repeating 16-bit
// patterns, 8-bit, 4-bit, and finally 2-bit.
unsigned hsb, lsb;
bool inverted;
if (findBitRange<32>(value, hsb, lsb, inverted))
return encodeLogicalImmediate<32>(hsb, lsb, inverted);
if ((value & 0xffff) != (value >> 16))
return InvalidLogicalImmediate;
value &= 0xffff;
if (findBitRange<16>(value, hsb, lsb, inverted))
return encodeLogicalImmediate<16>(hsb, lsb, inverted);
if ((value & 0xff) != (value >> 8))
return InvalidLogicalImmediate;
value &= 0xff;
if (findBitRange<8>(value, hsb, lsb, inverted))
return encodeLogicalImmediate<8>(hsb, lsb, inverted);
if ((value & 0xf) != (value >> 4))
return InvalidLogicalImmediate;
value &= 0xf;
if (findBitRange<4>(value, hsb, lsb, inverted))
return encodeLogicalImmediate<4>(hsb, lsb, inverted);
if ((value & 0x3) != (value >> 2))
return InvalidLogicalImmediate;
value &= 0x3;
if (findBitRange<2>(value, hsb, lsb, inverted))
return encodeLogicalImmediate<2>(hsb, lsb, inverted);
return InvalidLogicalImmediate;
}
static LogicalImmediate create64(uint64_t value)
{
// Check for 0, -1 - these cannot be encoded.
if (!value || !~value)
return InvalidLogicalImmediate;
// Look for a contiguous bit range.
unsigned hsb, lsb;
bool inverted;
if (findBitRange<64>(value, hsb, lsb, inverted))
return encodeLogicalImmediate<64>(hsb, lsb, inverted);
// If the high & low 32 bits are equal, we can try for a 32-bit (or narrower) pattern.
if (static_cast<uint32_t>(value) == static_cast<uint32_t>(value >> 32))
return create32(static_cast<uint32_t>(value));
return InvalidLogicalImmediate;
}
int value() const
{
ASSERT(isValid());
return m_value;
}
bool isValid() const
{
return m_value != InvalidLogicalImmediate;
}
bool is64bit() const
{
return m_value & (1 << 12);
}
private:
LogicalImmediate(int value)
: m_value(value)
{
}
// Generate a mask with bits in the range hsb..0 set, for example:
// hsb:63 = 0xffffffffffffffff
// hsb:42 = 0x000007ffffffffff
// hsb: 0 = 0x0000000000000001
static uint64_t mask(unsigned hsb)
{
ASSERT(hsb < 64);
return 0xffffffffffffffffull >> (63 - hsb);
}
template<unsigned N>
static void partialHSB(uint64_t& value, unsigned&result)
{
if (value & (0xffffffffffffffffull << N)) {
result += N;
value >>= N;
}
}
// Find the bit number of the highest bit set in a non-zero value, for example:
// 0x8080808080808080 = hsb:63
// 0x0000000000000001 = hsb: 0
// 0x000007ffffe00000 = hsb:42
static unsigned highestSetBit(uint64_t value)
{
ASSERT(value);
unsigned hsb = 0;
partialHSB<32>(value, hsb);
partialHSB<16>(value, hsb);
partialHSB<8>(value, hsb);
partialHSB<4>(value, hsb);
partialHSB<2>(value, hsb);
partialHSB<1>(value, hsb);
return hsb;
}
// This function takes a value and a bit width, where value obeys the following constraints:
// * bits outside of the width of the value must be zero.
// * bits within the width of value must neither be all clear or all set.
// The input is inspected to detect values that consist of either two or three contiguous
// ranges of bits. The output range hsb..lsb will describe the second range of the value.
// if the range is set, inverted will be false, and if the range is clear, inverted will
// be true. For example (with width 8):
// 00001111 = hsb:3, lsb:0, inverted:false
// 11110000 = hsb:3, lsb:0, inverted:true
// 00111100 = hsb:5, lsb:2, inverted:false
// 11000011 = hsb:5, lsb:2, inverted:true
template<unsigned width>
static bool findBitRange(uint64_t value, unsigned& hsb, unsigned& lsb, bool& inverted)
{
ASSERT(value & mask(width - 1));
ASSERT(value != mask(width - 1));
ASSERT(!(value & ~mask(width - 1)));
// Detect cases where the top bit is set; if so, flip all the bits & set invert.
// This halves the number of patterns we need to look for.
const uint64_t msb = 1ull << (width - 1);
if ((inverted = (value & msb)))
value ^= mask(width - 1);
// Find the highest set bit in value, generate a corresponding mask & flip all
// bits under it.
hsb = highestSetBit(value);
value ^= mask(hsb);
if (!value) {
// If this cleared the value, then the range hsb..0 was all set.
lsb = 0;
return true;
}
// Try making one more mask, and flipping the bits!
lsb = highestSetBit(value);
value ^= mask(lsb);
if (!value) {
// Success - but lsb actually points to the hsb of a third range - add one
// to get to the lsb of the mid range.
++lsb;
return true;
}
return false;
}
// Encodes the set of immN:immr:imms fields found in a logical immediate.
template<unsigned width>
static int encodeLogicalImmediate(unsigned hsb, unsigned lsb, bool inverted)
{
// Check width is a power of 2!
ASSERT(!(width & (width -1)));
ASSERT(width <= 64 && width >= 2);
ASSERT(hsb >= lsb);
ASSERT(hsb < width);
int immN = 0;
int imms = 0;
int immr = 0;
// For 64-bit values this is easy - just set immN to true, and imms just
// contains the bit number of the highest set bit of the set range. For
// values with narrower widths, these are encoded by a leading set of
// one bits, followed by a zero bit, followed by the remaining set of bits
// being the high bit of the range. For a 32-bit immediate there are no
// leading one bits, just a zero followed by a five bit number. For a
// 16-bit immediate there is one one bit, a zero bit, and then a four bit
// bit-position, etc.
if (width == 64)
immN = 1;
else
imms = 63 & ~(width + width - 1);
if (inverted) {
// if width is 64 & hsb is 62, then we have a value something like:
// 0x80000000ffffffff (in this case with lsb 32).
// The ror should be by 1, imms (effectively set width minus 1) is
// 32. Set width is full width minus cleared width.
immr = (width - 1) - hsb;
imms |= (width - ((hsb - lsb) + 1)) - 1;
} else {
// if width is 64 & hsb is 62, then we have a value something like:
// 0x7fffffff00000000 (in this case with lsb 32).
// The value is effectively rol'ed by lsb, which is equivalent to
// a ror by width - lsb (or 0, in the case where lsb is 0). imms
// is hsb - lsb.
immr = (width - lsb) & (width - 1);
imms |= hsb - lsb;
}
return immN << 12 | immr << 6 | imms;
}
static const int InvalidLogicalImmediate = -1;
int m_value;
};
inline uint16_t getHalfword(uint64_t value, int which)
{
return value >> (which << 4);
}
namespace ARM64Registers {
typedef enum {
// Parameter/result registers
x0,
x1,
x2,
x3,
x4,
x5,
x6,
x7,
// Indirect result location register
x8,
// Temporary registers
x9,
x10,
x11,
x12,
x13,
x14,
x15,
// Intra-procedure-call scratch registers (temporary)
x16, ip0 = x16,
x17, ip1 = x17,
// Platform Register (temporary)
x18,
// Callee-saved
x19,
x20,
x21,
x22,
x23,
x24,
x25,
x26,
x27,
x28,
// Special
x29, fp = x29,
x30, lr = x30,
sp,
zr = 0x3f,
} RegisterID;
typedef enum {
// Parameter/result registers
q0,
q1,
q2,
q3,
q4,
q5,
q6,
q7,
// Callee-saved (up to 64-bits only!)
q8,
q9,
q10,
q11,
q12,
q13,
q14,
q15,
// Temporary registers
q16,
q17,
q18,
q19,
q20,
q21,
q22,
q23,
q24,
q25,
q26,
q27,
q28,
q29,
q30,
q31,
} FPRegisterID;
static bool isSp(RegisterID reg) { return reg == sp; }
static bool isZr(RegisterID reg) { return reg == zr; }
}
class ARM64Assembler {
public:
typedef ARM64Registers::RegisterID RegisterID;
typedef ARM64Registers::FPRegisterID FPRegisterID;
static RegisterID firstRegister() { return ARM64Registers::x0; }
static RegisterID lastRegister() { return ARM64Registers::x28; }
static FPRegisterID firstFPRegister() { return ARM64Registers::q0; }
static FPRegisterID lastFPRegister() { return ARM64Registers::q31; }
private:
static bool isSp(RegisterID reg) { return ARM64Registers::isSp(reg); }
static bool isZr(RegisterID reg) { return ARM64Registers::isZr(reg); }
public:
ARM64Assembler()
: m_indexOfLastWatchpoint(INT_MIN)
, m_indexOfTailOfLastWatchpoint(INT_MIN)
{
}
AssemblerBuffer& buffer() { return m_buffer; }
// (HS, LO, HI, LS) -> (AE, B, A, BE)
// (VS, VC) -> (O, NO)
typedef enum {
ConditionEQ,
ConditionNE,
ConditionHS, ConditionCS = ConditionHS,
ConditionLO, ConditionCC = ConditionLO,
ConditionMI,
ConditionPL,
ConditionVS,
ConditionVC,
ConditionHI,
ConditionLS,
ConditionGE,
ConditionLT,
ConditionGT,
ConditionLE,
ConditionAL,
ConditionInvalid
} Condition;
static Condition invert(Condition cond)
{
return static_cast<Condition>(cond ^ 1);
}
typedef enum {
LSL,
LSR,
ASR,
ROR
} ShiftType;
typedef enum {
UXTB,
UXTH,
UXTW,
UXTX,
SXTB,
SXTH,
SXTW,
SXTX
} ExtendType;
enum SetFlags {
DontSetFlags,
S
};
#define JUMP_ENUM_WITH_SIZE(index, value) (((value) << 4) | (index))
#define JUMP_ENUM_SIZE(jump) ((jump) >> 4)
enum JumpType { JumpFixed = JUMP_ENUM_WITH_SIZE(0, 0),
JumpNoCondition = JUMP_ENUM_WITH_SIZE(1, 1 * sizeof(uint32_t)),
JumpCondition = JUMP_ENUM_WITH_SIZE(2, 2 * sizeof(uint32_t)),
JumpCompareAndBranch = JUMP_ENUM_WITH_SIZE(3, 2 * sizeof(uint32_t)),
JumpTestBit = JUMP_ENUM_WITH_SIZE(4, 2 * sizeof(uint32_t)),
JumpNoConditionFixedSize = JUMP_ENUM_WITH_SIZE(5, 1 * sizeof(uint32_t)),
JumpConditionFixedSize = JUMP_ENUM_WITH_SIZE(6, 2 * sizeof(uint32_t)),
JumpCompareAndBranchFixedSize = JUMP_ENUM_WITH_SIZE(7, 2 * sizeof(uint32_t)),
JumpTestBitFixedSize = JUMP_ENUM_WITH_SIZE(8, 2 * sizeof(uint32_t)),
};
enum JumpLinkType {
LinkInvalid = JUMP_ENUM_WITH_SIZE(0, 0),
LinkJumpNoCondition = JUMP_ENUM_WITH_SIZE(1, 1 * sizeof(uint32_t)),
LinkJumpConditionDirect = JUMP_ENUM_WITH_SIZE(2, 1 * sizeof(uint32_t)),
LinkJumpCondition = JUMP_ENUM_WITH_SIZE(3, 2 * sizeof(uint32_t)),
LinkJumpCompareAndBranch = JUMP_ENUM_WITH_SIZE(4, 2 * sizeof(uint32_t)),
LinkJumpCompareAndBranchDirect = JUMP_ENUM_WITH_SIZE(5, 1 * sizeof(uint32_t)),
LinkJumpTestBit = JUMP_ENUM_WITH_SIZE(6, 2 * sizeof(uint32_t)),
LinkJumpTestBitDirect = JUMP_ENUM_WITH_SIZE(7, 1 * sizeof(uint32_t)),
};
class LinkRecord {
public:
LinkRecord(intptr_t from, intptr_t to, JumpType type, Condition condition)
{
data.realTypes.m_from = from;
data.realTypes.m_to = to;
data.realTypes.m_type = type;
data.realTypes.m_linkType = LinkInvalid;
data.realTypes.m_condition = condition;
}
LinkRecord(intptr_t from, intptr_t to, JumpType type, Condition condition, bool is64Bit, RegisterID compareRegister)
{
data.realTypes.m_from = from;
data.realTypes.m_to = to;
data.realTypes.m_type = type;
data.realTypes.m_linkType = LinkInvalid;
data.realTypes.m_condition = condition;
data.realTypes.m_is64Bit = is64Bit;
data.realTypes.m_compareRegister = compareRegister;
}
LinkRecord(intptr_t from, intptr_t to, JumpType type, Condition condition, unsigned bitNumber, RegisterID compareRegister)
{
data.realTypes.m_from = from;
data.realTypes.m_to = to;
data.realTypes.m_type = type;
data.realTypes.m_linkType = LinkInvalid;
data.realTypes.m_condition = condition;
data.realTypes.m_bitNumber = bitNumber;
data.realTypes.m_compareRegister = compareRegister;
}
void operator=(const LinkRecord& other)
{
data.copyTypes.content[0] = other.data.copyTypes.content[0];
data.copyTypes.content[1] = other.data.copyTypes.content[1];
data.copyTypes.content[2] = other.data.copyTypes.content[2];
}
intptr_t from() const { return data.realTypes.m_from; }
void setFrom(intptr_t from) { data.realTypes.m_from = from; }
intptr_t to() const { return data.realTypes.m_to; }
JumpType type() const { return data.realTypes.m_type; }
JumpLinkType linkType() const { return data.realTypes.m_linkType; }
void setLinkType(JumpLinkType linkType) { ASSERT(data.realTypes.m_linkType == LinkInvalid); data.realTypes.m_linkType = linkType; }
Condition condition() const { return data.realTypes.m_condition; }
bool is64Bit() const { return data.realTypes.m_is64Bit; }
unsigned bitNumber() const { return data.realTypes.m_bitNumber; }
RegisterID compareRegister() const { return data.realTypes.m_compareRegister; }
private:
union {
struct RealTypes {
intptr_t m_from : 48;
intptr_t m_to : 48;
JumpType m_type : 8;
JumpLinkType m_linkType : 8;
Condition m_condition : 4;
bool m_is64Bit : 1;
unsigned m_bitNumber : 6;
RegisterID m_compareRegister : 5;
} realTypes;
struct CopyTypes {
uint64_t content[3];
} copyTypes;
COMPILE_ASSERT(sizeof(RealTypes) == sizeof(CopyTypes), LinkRecordCopyStructSizeEqualsRealStruct);
} data;
};
// bits(N) VFPExpandImm(bits(8) imm8);
//
// Encoding of floating point immediates is a litte complicated. Here's a
// high level description:
// +/-m*2-n where m and n are integers, 16 <= m <= 31, 0 <= n <= 7
// and the algirithm for expanding to a single precision float:
// return imm8<7>:NOT(imm8<6>):Replicate(imm8<6>,5):imm8<5:0>:Zeros(19);
//
// The trickiest bit is how the exponent is handled. The following table
// may help clarify things a little:
// 654
// 100 01111100 124 -3 1020 01111111100
// 101 01111101 125 -2 1021 01111111101
// 110 01111110 126 -1 1022 01111111110
// 111 01111111 127 0 1023 01111111111
// 000 10000000 128 1 1024 10000000000
// 001 10000001 129 2 1025 10000000001
// 010 10000010 130 3 1026 10000000010
// 011 10000011 131 4 1027 10000000011
// The first column shows the bit pattern stored in bits 6-4 of the arm
// encoded immediate. The second column shows the 8-bit IEEE 754 single
// -precision exponent in binary, the third column shows the raw decimal
// value. IEEE 754 single-precision numbers are stored with a bias of 127
// to the exponent, so the fourth column shows the resulting exponent.
// From this was can see that the exponent can be in the range -3..4,
// which agrees with the high level description given above. The fifth
// and sixth columns shows the value stored in a IEEE 754 double-precision
// number to represent these exponents in decimal and binary, given the
// bias of 1023.
//
// Ultimately, detecting doubles that can be encoded as immediates on arm
// and encoding doubles is actually not too bad. A floating point value can
// be encoded by retaining the sign bit, the low three bits of the exponent
// and the high 4 bits of the mantissa. To validly be able to encode an
// immediate the remainder of the mantissa must be zero, and the high part
// of the exponent must match the top bit retained, bar the highest bit
// which must be its inverse.
static bool canEncodeFPImm(double d)
{
// Discard the sign bit, the low two bits of the exponent & the highest
// four bits of the mantissa.
uint64_t masked = bitwise_cast<uint64_t>(d) & 0x7fc0ffffffffffffull;
return (masked == 0x3fc0000000000000ull) || (masked == 0x4000000000000000ull);
}
template<int datasize>
static bool canEncodePImmOffset(int32_t offset)
{
int32_t maxPImm = 4095 * (datasize / 8);
if (offset < 0)
return false;
if (offset > maxPImm)
return false;
if (offset & ((datasize / 8 ) - 1))
return false;
return true;
}
static bool canEncodeSImmOffset(int32_t offset)
{
return isInt9(offset);
}
private:
int encodeFPImm(double d)
{
ASSERT(canEncodeFPImm(d));
uint64_t u64 = bitwise_cast<uint64_t>(d);
return (static_cast<int>(u64 >> 56) & 0x80) | (static_cast<int>(u64 >> 48) & 0x7f);
}
template<int datasize>
int encodeShiftAmount(int amount)
{
ASSERT(!amount || datasize == (8 << amount));
return amount;
}
template<int datasize>
static int encodePositiveImmediate(unsigned pimm)
{
ASSERT(!(pimm & ((datasize / 8) - 1)));
return pimm / (datasize / 8);
}
enum Datasize {
Datasize_32,
Datasize_64,
Datasize_64_top,
Datasize_16
};
enum MemOpSize {
MemOpSize_8_or_128,
MemOpSize_16,
MemOpSize_32,
MemOpSize_64,
};
enum BranchType {
BranchType_JMP,
BranchType_CALL,
BranchType_RET
};
enum AddOp {
AddOp_ADD,
AddOp_SUB
};
enum BitfieldOp {
BitfieldOp_SBFM,
BitfieldOp_BFM,
BitfieldOp_UBFM
};
enum DataOp1Source {
DataOp_RBIT,
DataOp_REV16,
DataOp_REV32,
DataOp_REV64,
DataOp_CLZ,
DataOp_CLS
};
enum DataOp2Source {
DataOp_UDIV = 2,
DataOp_SDIV = 3,
DataOp_LSLV = 8,
DataOp_LSRV = 9,
DataOp_ASRV = 10,
DataOp_RORV = 11
};
enum DataOp3Source {
DataOp_MADD = 0,
DataOp_MSUB = 1,
DataOp_SMADDL = 2,
DataOp_SMSUBL = 3,
DataOp_SMULH = 4,
DataOp_UMADDL = 10,
DataOp_UMSUBL = 11,
DataOp_UMULH = 12
};
enum ExcepnOp {
ExcepnOp_EXCEPTION = 0,
ExcepnOp_BREAKPOINT = 1,
ExcepnOp_HALT = 2,
ExcepnOp_DCPS = 5
};
enum FPCmpOp {
FPCmpOp_FCMP = 0x00,
FPCmpOp_FCMP0 = 0x08,
FPCmpOp_FCMPE = 0x10,
FPCmpOp_FCMPE0 = 0x18
};
enum FPCondCmpOp {
FPCondCmpOp_FCMP,
FPCondCmpOp_FCMPE
};
enum FPDataOp1Source {
FPDataOp_FMOV = 0,
FPDataOp_FABS = 1,
FPDataOp_FNEG = 2,
FPDataOp_FSQRT = 3,
FPDataOp_FCVT_toSingle = 4,
FPDataOp_FCVT_toDouble = 5,
FPDataOp_FCVT_toHalf = 7,
FPDataOp_FRINTN = 8,
FPDataOp_FRINTP = 9,
FPDataOp_FRINTM = 10,
FPDataOp_FRINTZ = 11,
FPDataOp_FRINTA = 12,
FPDataOp_FRINTX = 14,
FPDataOp_FRINTI = 15
};
enum FPDataOp2Source {
FPDataOp_FMUL,
FPDataOp_FDIV,
FPDataOp_FADD,
FPDataOp_FSUB,
FPDataOp_FMAX,
FPDataOp_FMIN,
FPDataOp_FMAXNM,
FPDataOp_FMINNM,
FPDataOp_FNMUL
};
enum FPIntConvOp {
FPIntConvOp_FCVTNS = 0x00,
FPIntConvOp_FCVTNU = 0x01,
FPIntConvOp_SCVTF = 0x02,
FPIntConvOp_UCVTF = 0x03,
FPIntConvOp_FCVTAS = 0x04,
FPIntConvOp_FCVTAU = 0x05,
FPIntConvOp_FMOV_QtoX = 0x06,
FPIntConvOp_FMOV_XtoQ = 0x07,
FPIntConvOp_FCVTPS = 0x08,
FPIntConvOp_FCVTPU = 0x09,
FPIntConvOp_FMOV_QtoX_top = 0x0e,
FPIntConvOp_FMOV_XtoQ_top = 0x0f,
FPIntConvOp_FCVTMS = 0x10,
FPIntConvOp_FCVTMU = 0x11,
FPIntConvOp_FCVTZS = 0x18,
FPIntConvOp_FCVTZU = 0x19,
};
enum LogicalOp {
LogicalOp_AND,
LogicalOp_ORR,
LogicalOp_EOR,
LogicalOp_ANDS
};
enum MemOp {
MemOp_STORE,
MemOp_LOAD,
MemOp_STORE_V128,
MemOp_LOAD_V128,
MemOp_PREFETCH = 2, // size must be 3
MemOp_LOAD_signed64 = 2, // size may be 0, 1 or 2
MemOp_LOAD_signed32 = 3 // size may be 0 or 1
};
enum MoveWideOp {
MoveWideOp_N = 0,
MoveWideOp_Z = 2,
MoveWideOp_K = 3
};
enum LdrLiteralOp {
LdrLiteralOp_32BIT = 0,
LdrLiteralOp_64BIT = 1,
LdrLiteralOp_LDRSW = 2,
LdrLiteralOp_128BIT = 2
};
public:
// Integer Instructions:
template<int datasize, SetFlags setFlags = DontSetFlags>
ALWAYS_INLINE void adc(RegisterID rd, RegisterID rn, RegisterID rm)
{
CHECK_DATASIZE();
insn(addSubtractWithCarry(DATASIZE, AddOp_ADD, setFlags, rm, rn, rd));
}
template<int datasize, SetFlags setFlags = DontSetFlags>
ALWAYS_INLINE void add(RegisterID rd, RegisterID rn, UInt12 imm12, int shift = 0)
{
CHECK_DATASIZE();
ASSERT(!shift || shift == 12);
insn(addSubtractImmediate(DATASIZE, AddOp_ADD, setFlags, shift == 12, imm12, rn, rd));
}
template<int datasize, SetFlags setFlags = DontSetFlags>
ALWAYS_INLINE void add(RegisterID rd, RegisterID rn, RegisterID rm)
{
add<datasize, setFlags>(rd, rn, rm, LSL, 0);
}
template<int datasize, SetFlags setFlags = DontSetFlags>
ALWAYS_INLINE void add(RegisterID rd, RegisterID rn, RegisterID rm, ExtendType extend, int amount)
{
CHECK_DATASIZE();
insn(addSubtractExtendedRegister(DATASIZE, AddOp_ADD, setFlags, rm, extend, amount, rn, rd));
}
template<int datasize, SetFlags setFlags = DontSetFlags>
ALWAYS_INLINE void add(RegisterID rd, RegisterID rn, RegisterID rm, ShiftType shift, int amount)
{
CHECK_DATASIZE();
if (isSp(rn)) {
ASSERT(shift == LSL);
add<datasize, setFlags>(rd, rn, rm, UXTX, amount);
} else
insn(addSubtractShiftedRegister(DATASIZE, AddOp_ADD, setFlags, shift, rm, amount, rn, rd));
}
ALWAYS_INLINE void adr(RegisterID rd, int offset)
{
insn(pcRelative(false, offset, rd));
}
ALWAYS_INLINE void adrp(RegisterID rd, int offset)
{
ASSERT(!(offset & 0xfff));
insn(pcRelative(true, offset >> 12, rd));
}
template<int datasize, SetFlags setFlags = DontSetFlags>
ALWAYS_INLINE void and_(RegisterID rd, RegisterID rn, RegisterID rm)
{
and_<datasize, setFlags>(rd, rn, rm, LSL, 0);
}
template<int datasize, SetFlags setFlags = DontSetFlags>
ALWAYS_INLINE void and_(RegisterID rd, RegisterID rn, RegisterID rm, ShiftType shift, int amount)
{
CHECK_DATASIZE();
insn(logicalShiftedRegister(DATASIZE, setFlags ? LogicalOp_ANDS : LogicalOp_AND, shift, false, rm, amount, rn, rd));
}
template<int datasize, SetFlags setFlags = DontSetFlags>
ALWAYS_INLINE void and_(RegisterID rd, RegisterID rn, LogicalImmediate imm)
{
CHECK_DATASIZE();
insn(logicalImmediate(DATASIZE, setFlags ? LogicalOp_ANDS : LogicalOp_AND, imm.value(), rn, rd));
}
template<int datasize>
ALWAYS_INLINE void asr(RegisterID rd, RegisterID rn, int shift)
{
ASSERT(shift < datasize);
sbfm<datasize>(rd, rn, shift, datasize - 1);
}
template<int datasize>
ALWAYS_INLINE void asr(RegisterID rd, RegisterID rn, RegisterID rm)
{
asrv<datasize>(rd, rn, rm);
}
template<int datasize>
ALWAYS_INLINE void asrv(RegisterID rd, RegisterID rn, RegisterID rm)
{
CHECK_DATASIZE();
insn(dataProcessing2Source(DATASIZE, rm, DataOp_ASRV, rn, rd));
}
ALWAYS_INLINE void b(int32_t offset = 0)
{
ASSERT(!(offset & 3));
offset >>= 2;
ASSERT(offset == (offset << 6) >> 6);
insn(unconditionalBranchImmediate(false, offset));
}
ALWAYS_INLINE void b_cond(Condition cond, int32_t offset = 0)
{
ASSERT(!(offset & 3));
offset >>= 2;
ASSERT(offset == (offset << 13) >> 13);
insn(conditionalBranchImmediate(offset, cond));
}
template<int datasize>
ALWAYS_INLINE void bfi(RegisterID rd, RegisterID rn, int lsb, int width)
{
bfm<datasize>(rd, rn, (datasize - lsb) & (datasize - 1), width - 1);
}
template<int datasize>
ALWAYS_INLINE void bfm(RegisterID rd, RegisterID rn, int immr, int imms)
{
CHECK_DATASIZE();
insn(bitfield(DATASIZE, BitfieldOp_BFM, immr, imms, rn, rd));
}
template<int datasize>
ALWAYS_INLINE void bfxil(RegisterID rd, RegisterID rn, int lsb, int width)
{
bfm<datasize>(rd, rn, lsb, lsb + width - 1);
}
template<int datasize, SetFlags setFlags = DontSetFlags>
ALWAYS_INLINE void bic(RegisterID rd, RegisterID rn, RegisterID rm)
{
bic<datasize, setFlags>(rd, rn, rm, LSL, 0);
}
template<int datasize, SetFlags setFlags = DontSetFlags>
ALWAYS_INLINE void bic(RegisterID rd, RegisterID rn, RegisterID rm, ShiftType shift, int amount)
{
CHECK_DATASIZE();
insn(logicalShiftedRegister(DATASIZE, setFlags ? LogicalOp_ANDS : LogicalOp_AND, shift, true, rm, amount, rn, rd));
}
ALWAYS_INLINE void bl(int32_t offset = 0)
{
ASSERT(!(offset & 3));
offset >>= 2;
insn(unconditionalBranchImmediate(true, offset));
}
ALWAYS_INLINE void blr(RegisterID rn)
{
insn(unconditionalBranchRegister(BranchType_CALL, rn));
}
ALWAYS_INLINE void br(RegisterID rn)
{
insn(unconditionalBranchRegister(BranchType_JMP, rn));
}
ALWAYS_INLINE void brk(uint16_t imm)
{
insn(excepnGeneration(ExcepnOp_BREAKPOINT, imm, 0));
}