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SH4Assembler.h
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2080 lines (1841 loc) · 57.9 KB
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/*
* Copyright (C) 2009-2011 STMicroelectronics. All rights reserved.
* Copyright (C) 2008 Apple Inc. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY APPLE INC. ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL APPLE INC. OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
* OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef SH4Assembler_h
#define SH4Assembler_h
#if ENABLE(ASSEMBLER) && CPU(SH4)
#include "AssemblerBuffer.h"
#include "AssemblerBufferWithConstantPool.h"
#include "JITCompilationEffort.h"
#include <stdarg.h>
#include <stdint.h>
#include <stdio.h>
#include <wtf/Assertions.h>
#include <wtf/DataLog.h>
#include <wtf/Vector.h>
#ifndef NDEBUG
#define SH4_ASSEMBLER_TRACING
#endif
namespace JSC {
typedef uint16_t SH4Word;
enum {
INVALID_OPCODE = 0xffff,
ADD_OPCODE = 0x300c,
ADDIMM_OPCODE = 0x7000,
ADDC_OPCODE = 0x300e,
ADDV_OPCODE = 0x300f,
AND_OPCODE = 0x2009,
ANDIMM_OPCODE = 0xc900,
DIV0_OPCODE = 0x2007,
DIV1_OPCODE = 0x3004,
BF_OPCODE = 0x8b00,
BFS_OPCODE = 0x8f00,
BRA_OPCODE = 0xa000,
BRAF_OPCODE = 0x0023,
NOP_OPCODE = 0x0009,
BSR_OPCODE = 0xb000,
RTS_OPCODE = 0x000b,
BT_OPCODE = 0x8900,
BTS_OPCODE = 0x8d00,
BSRF_OPCODE = 0x0003,
BRK_OPCODE = 0x003b,
FTRC_OPCODE = 0xf03d,
CMPEQ_OPCODE = 0x3000,
CMPEQIMM_OPCODE = 0x8800,
CMPGE_OPCODE = 0x3003,
CMPGT_OPCODE = 0x3007,
CMPHI_OPCODE = 0x3006,
CMPHS_OPCODE = 0x3002,
CMPPL_OPCODE = 0x4015,
CMPPZ_OPCODE = 0x4011,
CMPSTR_OPCODE = 0x200c,
DT_OPCODE = 0x4010,
FCMPEQ_OPCODE = 0xf004,
FCMPGT_OPCODE = 0xf005,
FMOV_OPCODE = 0xf00c,
FADD_OPCODE = 0xf000,
FMUL_OPCODE = 0xf002,
FSUB_OPCODE = 0xf001,
FDIV_OPCODE = 0xf003,
FNEG_OPCODE = 0xf04d,
JMP_OPCODE = 0x402b,
JSR_OPCODE = 0x400b,
LDSPR_OPCODE = 0x402a,
LDSLPR_OPCODE = 0x4026,
MOV_OPCODE = 0x6003,
MOVIMM_OPCODE = 0xe000,
MOVB_WRITE_RN_OPCODE = 0x2000,
MOVB_WRITE_RNDEC_OPCODE = 0x2004,
MOVB_WRITE_R0RN_OPCODE = 0x0004,
MOVB_WRITE_OFFGBR_OPCODE = 0xc000,
MOVB_WRITE_OFFRN_OPCODE = 0x8000,
MOVB_READ_RM_OPCODE = 0x6000,
MOVB_READ_RMINC_OPCODE = 0x6004,
MOVB_READ_R0RM_OPCODE = 0x000c,
MOVB_READ_OFFGBR_OPCODE = 0xc400,
MOVB_READ_OFFRM_OPCODE = 0x8400,
MOVL_WRITE_RN_OPCODE = 0x2002,
MOVL_WRITE_RNDEC_OPCODE = 0x2006,
MOVL_WRITE_R0RN_OPCODE = 0x0006,
MOVL_WRITE_OFFGBR_OPCODE = 0xc200,
MOVL_WRITE_OFFRN_OPCODE = 0x1000,
MOVL_READ_RM_OPCODE = 0x6002,
MOVL_READ_RMINC_OPCODE = 0x6006,
MOVL_READ_R0RM_OPCODE = 0x000e,
MOVL_READ_OFFGBR_OPCODE = 0xc600,
MOVL_READ_OFFPC_OPCODE = 0xd000,
MOVL_READ_OFFRM_OPCODE = 0x5000,
MOVW_WRITE_RN_OPCODE = 0x2001,
MOVW_READ_RM_OPCODE = 0x6001,
MOVW_READ_R0RM_OPCODE = 0x000d,
MOVW_READ_OFFRM_OPCODE = 0x8500,
MOVW_READ_OFFPC_OPCODE = 0x9000,
MOVA_READ_OFFPC_OPCODE = 0xc700,
MOVT_OPCODE = 0x0029,
MULL_OPCODE = 0x0007,
DMULL_L_OPCODE = 0x3005,
STSMACL_OPCODE = 0x001a,
STSMACH_OPCODE = 0x000a,
DMULSL_OPCODE = 0x300d,
NEG_OPCODE = 0x600b,
NEGC_OPCODE = 0x600a,
NOT_OPCODE = 0x6007,
OR_OPCODE = 0x200b,
ORIMM_OPCODE = 0xcb00,
ORBIMM_OPCODE = 0xcf00,
SETS_OPCODE = 0x0058,
SETT_OPCODE = 0x0018,
SHAD_OPCODE = 0x400c,
SHAL_OPCODE = 0x4020,
SHAR_OPCODE = 0x4021,
SHLD_OPCODE = 0x400d,
SHLL_OPCODE = 0x4000,
SHLL2_OPCODE = 0x4008,
SHLL8_OPCODE = 0x4018,
SHLL16_OPCODE = 0x4028,
SHLR_OPCODE = 0x4001,
SHLR2_OPCODE = 0x4009,
SHLR8_OPCODE = 0x4019,
SHLR16_OPCODE = 0x4029,
STSPR_OPCODE = 0x002a,
STSLPR_OPCODE = 0x4022,
FLOAT_OPCODE = 0xf02d,
SUB_OPCODE = 0x3008,
SUBC_OPCODE = 0x300a,
SUBV_OPCODE = 0x300b,
TST_OPCODE = 0x2008,
TSTIMM_OPCODE = 0xc800,
TSTB_OPCODE = 0xcc00,
EXTUB_OPCODE = 0x600c,
EXTUW_OPCODE = 0x600d,
XOR_OPCODE = 0x200a,
XORIMM_OPCODE = 0xca00,
XORB_OPCODE = 0xce00,
FMOVS_READ_RM_INC_OPCODE = 0xf009,
FMOVS_READ_RM_OPCODE = 0xf008,
FMOVS_READ_R0RM_OPCODE = 0xf006,
FMOVS_WRITE_RN_OPCODE = 0xf00a,
FMOVS_WRITE_RN_DEC_OPCODE = 0xf00b,
FMOVS_WRITE_R0RN_OPCODE = 0xf007,
FCNVDS_DRM_FPUL_OPCODE = 0xf0bd,
LDS_RM_FPUL_OPCODE = 0x405a,
FLDS_FRM_FPUL_OPCODE = 0xf01d,
STS_FPUL_RN_OPCODE = 0x005a,
FSTS_FPUL_FRN_OPCODE = 0xF00d,
LDSFPSCR_OPCODE = 0x406a,
STSFPSCR_OPCODE = 0x006a,
LDSRMFPUL_OPCODE = 0x405a,
FSTSFPULFRN_OPCODE = 0xf00d,
FSQRT_OPCODE = 0xf06d,
FSCHG_OPCODE = 0xf3fd,
CLRT_OPCODE = 8,
};
namespace SH4Registers {
typedef enum {
r0,
r1,
r2,
r3,
r4,
r5,
r6,
r7,
r8,
r9,
r10,
r11,
r12,
r13,
r14, fp = r14,
r15, sp = r15,
pc,
pr,
} RegisterID;
typedef enum {
fr0, dr0 = fr0,
fr1,
fr2, dr2 = fr2,
fr3,
fr4, dr4 = fr4,
fr5,
fr6, dr6 = fr6,
fr7,
fr8, dr8 = fr8,
fr9,
fr10, dr10 = fr10,
fr11,
fr12, dr12 = fr12,
fr13,
fr14, dr14 = fr14,
fr15,
} FPRegisterID;
}
inline uint16_t getOpcodeGroup1(uint16_t opc, int rm, int rn)
{
return (opc | ((rm & 0xf) << 8) | ((rn & 0xf) << 4));
}
inline uint16_t getOpcodeGroup2(uint16_t opc, int rm)
{
return (opc | ((rm & 0xf) << 8));
}
inline uint16_t getOpcodeGroup3(uint16_t opc, int rm, int rn)
{
return (opc | ((rm & 0xf) << 8) | (rn & 0xff));
}
inline uint16_t getOpcodeGroup4(uint16_t opc, int rm, int rn, int offset)
{
return (opc | ((rm & 0xf) << 8) | ((rn & 0xf) << 4) | (offset & 0xf));
}
inline uint16_t getOpcodeGroup5(uint16_t opc, int rm)
{
return (opc | (rm & 0xff));
}
inline uint16_t getOpcodeGroup6(uint16_t opc, int rm)
{
return (opc | (rm & 0xfff));
}
inline uint16_t getOpcodeGroup7(uint16_t opc, int rm)
{
return (opc | ((rm & 0x7) << 9));
}
inline uint16_t getOpcodeGroup8(uint16_t opc, int rm, int rn)
{
return (opc | ((rm & 0x7) << 9) | ((rn & 0x7) << 5));
}
inline uint16_t getOpcodeGroup9(uint16_t opc, int rm, int rn)
{
return (opc | ((rm & 0xf) << 8) | ((rn & 0x7) << 5));
}
inline uint16_t getOpcodeGroup10(uint16_t opc, int rm, int rn)
{
return (opc | ((rm & 0x7) << 9) | ((rn & 0xf) << 4));
}
inline uint16_t getOpcodeGroup11(uint16_t opc, int rm, int rn)
{
return (opc | ((rm & 0xf) << 4) | (rn & 0xf));
}
inline uint16_t getRn(uint16_t x)
{
return ((x & 0xf00) >> 8);
}
inline uint16_t getRm(uint16_t x)
{
return ((x & 0xf0) >> 4);
}
inline uint16_t getDisp(uint16_t x)
{
return (x & 0xf);
}
inline uint16_t getImm8(uint16_t x)
{
return (x & 0xff);
}
inline uint16_t getImm12(uint16_t x)
{
return (x & 0xfff);
}
inline uint16_t getDRn(uint16_t x)
{
return ((x & 0xe00) >> 9);
}
inline uint16_t getDRm(uint16_t x)
{
return ((x & 0xe0) >> 5);
}
class SH4Assembler {
public:
typedef SH4Registers::RegisterID RegisterID;
typedef SH4Registers::FPRegisterID FPRegisterID;
typedef AssemblerBufferWithConstantPool<512, 4, 2, SH4Assembler> SH4Buffer;
static const RegisterID scratchReg1 = SH4Registers::r3;
static const RegisterID scratchReg2 = SH4Registers::r11;
static const uint32_t maxInstructionSize = 16;
enum {
padForAlign8 = 0x00,
padForAlign16 = 0x0009,
padForAlign32 = 0x00090009,
};
enum JumpType { JumpFar,
JumpNear
};
SH4Assembler()
{
m_claimscratchReg = 0x0;
}
// SH4 condition codes
typedef enum {
EQ = 0x0, // Equal
NE = 0x1, // Not Equal
HS = 0x2, // Unsigend Greater Than equal
HI = 0x3, // Unsigend Greater Than
LS = 0x4, // Unsigend Lower or Same
LI = 0x5, // Unsigend Lower
GE = 0x6, // Greater or Equal
LT = 0x7, // Less Than
GT = 0x8, // Greater Than
LE = 0x9, // Less or Equal
OF = 0xa, // OverFlow
SI = 0xb, // Signed
EQU= 0xc, // Equal or unordered(NaN)
NEU= 0xd,
GTU= 0xe,
GEU= 0xf,
LTU= 0x10,
LEU= 0x11,
} Condition;
// Opaque label types
public:
bool isImmediate(int constant)
{
return ((constant <= 127) && (constant >= -128));
}
RegisterID claimScratch()
{
ASSERT((m_claimscratchReg != 0x3));
if (!(m_claimscratchReg & 0x1)) {
m_claimscratchReg = (m_claimscratchReg | 0x1);
return scratchReg1;
}
m_claimscratchReg = (m_claimscratchReg | 0x2);
return scratchReg2;
}
void releaseScratch(RegisterID scratchR)
{
if (scratchR == scratchReg1)
m_claimscratchReg = (m_claimscratchReg & 0x2);
else
m_claimscratchReg = (m_claimscratchReg & 0x1);
}
// Stack operations
void pushReg(RegisterID reg)
{
if (reg == SH4Registers::pr) {
oneShortOp(getOpcodeGroup2(STSLPR_OPCODE, SH4Registers::sp));
return;
}
oneShortOp(getOpcodeGroup1(MOVL_WRITE_RNDEC_OPCODE, SH4Registers::sp, reg));
}
void popReg(RegisterID reg)
{
if (reg == SH4Registers::pr) {
oneShortOp(getOpcodeGroup2(LDSLPR_OPCODE, SH4Registers::sp));
return;
}
oneShortOp(getOpcodeGroup1(MOVL_READ_RMINC_OPCODE, reg, SH4Registers::sp));
}
void movt(RegisterID dst)
{
uint16_t opc = getOpcodeGroup2(MOVT_OPCODE, dst);
oneShortOp(opc);
}
// Arithmetic operations
void addlRegReg(RegisterID src, RegisterID dst)
{
uint16_t opc = getOpcodeGroup1(ADD_OPCODE, dst, src);
oneShortOp(opc);
}
void addclRegReg(RegisterID src, RegisterID dst)
{
uint16_t opc = getOpcodeGroup1(ADDC_OPCODE, dst, src);
oneShortOp(opc);
}
void addvlRegReg(RegisterID src, RegisterID dst)
{
uint16_t opc = getOpcodeGroup1(ADDV_OPCODE, dst, src);
oneShortOp(opc);
}
void addlImm8r(int imm8, RegisterID dst)
{
ASSERT((imm8 <= 127) && (imm8 >= -128));
uint16_t opc = getOpcodeGroup3(ADDIMM_OPCODE, dst, imm8);
oneShortOp(opc);
}
void andlRegReg(RegisterID src, RegisterID dst)
{
uint16_t opc = getOpcodeGroup1(AND_OPCODE, dst, src);
oneShortOp(opc);
}
void andlImm8r(int imm8, RegisterID dst)
{
ASSERT((imm8 <= 255) && (imm8 >= 0));
ASSERT(dst == SH4Registers::r0);
uint16_t opc = getOpcodeGroup5(ANDIMM_OPCODE, imm8);
oneShortOp(opc);
}
void div1lRegReg(RegisterID src, RegisterID dst)
{
uint16_t opc = getOpcodeGroup1(DIV1_OPCODE, dst, src);
oneShortOp(opc);
}
void div0lRegReg(RegisterID src, RegisterID dst)
{
uint16_t opc = getOpcodeGroup1(DIV0_OPCODE, dst, src);
oneShortOp(opc);
}
void notlReg(RegisterID src, RegisterID dst)
{
uint16_t opc = getOpcodeGroup1(NOT_OPCODE, dst, src);
oneShortOp(opc);
}
void orlRegReg(RegisterID src, RegisterID dst)
{
uint16_t opc = getOpcodeGroup1(OR_OPCODE, dst, src);
oneShortOp(opc);
}
void orlImm8r(int imm8, RegisterID dst)
{
ASSERT((imm8 <= 255) && (imm8 >= 0));
ASSERT(dst == SH4Registers::r0);
uint16_t opc = getOpcodeGroup5(ORIMM_OPCODE, imm8);
oneShortOp(opc);
}
void sublRegReg(RegisterID src, RegisterID dst)
{
uint16_t opc = getOpcodeGroup1(SUB_OPCODE, dst, src);
oneShortOp(opc);
}
void subvlRegReg(RegisterID src, RegisterID dst)
{
uint16_t opc = getOpcodeGroup1(SUBV_OPCODE, dst, src);
oneShortOp(opc);
}
void xorlRegReg(RegisterID src, RegisterID dst)
{
uint16_t opc = getOpcodeGroup1(XOR_OPCODE, dst, src);
oneShortOp(opc);
}
void xorlImm8r(int imm8, RegisterID dst)
{
ASSERT((imm8 <= 255) && (imm8 >= 0));
ASSERT(dst == SH4Registers::r0);
uint16_t opc = getOpcodeGroup5(XORIMM_OPCODE, imm8);
oneShortOp(opc);
}
void shllImm8r(int imm, RegisterID dst)
{
switch (imm) {
case 1:
oneShortOp(getOpcodeGroup2(SHLL_OPCODE, dst));
break;
case 2:
oneShortOp(getOpcodeGroup2(SHLL2_OPCODE, dst));
break;
case 8:
oneShortOp(getOpcodeGroup2(SHLL8_OPCODE, dst));
break;
case 16:
oneShortOp(getOpcodeGroup2(SHLL16_OPCODE, dst));
break;
default:
ASSERT_NOT_REACHED();
}
}
void neg(RegisterID dst, RegisterID src)
{
uint16_t opc = getOpcodeGroup1(NEG_OPCODE, dst, src);
oneShortOp(opc);
}
void shllRegReg(RegisterID dst, RegisterID rShift)
{
uint16_t opc = getOpcodeGroup1(SHLD_OPCODE, dst, rShift);
oneShortOp(opc);
}
void shlrRegReg(RegisterID dst, RegisterID rShift)
{
neg(rShift, rShift);
shllRegReg(dst, rShift);
}
void sharRegReg(RegisterID dst, RegisterID rShift)
{
neg(rShift, rShift);
shaRegReg(dst, rShift);
}
void shaRegReg(RegisterID dst, RegisterID rShift)
{
uint16_t opc = getOpcodeGroup1(SHAD_OPCODE, dst, rShift);
oneShortOp(opc);
}
void shlrImm8r(int imm, RegisterID dst)
{
switch (imm) {
case 1:
oneShortOp(getOpcodeGroup2(SHLR_OPCODE, dst));
break;
case 2:
oneShortOp(getOpcodeGroup2(SHLR2_OPCODE, dst));
break;
case 8:
oneShortOp(getOpcodeGroup2(SHLR8_OPCODE, dst));
break;
case 16:
oneShortOp(getOpcodeGroup2(SHLR16_OPCODE, dst));
break;
default:
ASSERT_NOT_REACHED();
}
}
void imullRegReg(RegisterID src, RegisterID dst)
{
uint16_t opc = getOpcodeGroup1(MULL_OPCODE, dst, src);
oneShortOp(opc);
}
void dmullRegReg(RegisterID src, RegisterID dst)
{
uint16_t opc = getOpcodeGroup1(DMULL_L_OPCODE, dst, src);
oneShortOp(opc);
}
void dmulslRegReg(RegisterID src, RegisterID dst)
{
uint16_t opc = getOpcodeGroup1(DMULSL_OPCODE, dst, src);
oneShortOp(opc);
}
void stsmacl(RegisterID reg)
{
uint16_t opc = getOpcodeGroup2(STSMACL_OPCODE, reg);
oneShortOp(opc);
}
void stsmach(RegisterID reg)
{
uint16_t opc = getOpcodeGroup2(STSMACH_OPCODE, reg);
oneShortOp(opc);
}
// Comparisons
void cmplRegReg(RegisterID left, RegisterID right, Condition cond)
{
switch (cond) {
case NE:
oneShortOp(getOpcodeGroup1(CMPEQ_OPCODE, right, left));
break;
case GT:
oneShortOp(getOpcodeGroup1(CMPGT_OPCODE, right, left));
break;
case EQ:
oneShortOp(getOpcodeGroup1(CMPEQ_OPCODE, right, left));
break;
case GE:
oneShortOp(getOpcodeGroup1(CMPGE_OPCODE, right, left));
break;
case HS:
oneShortOp(getOpcodeGroup1(CMPHS_OPCODE, right, left));
break;
case HI:
oneShortOp(getOpcodeGroup1(CMPHI_OPCODE, right, left));
break;
case LI:
oneShortOp(getOpcodeGroup1(CMPHI_OPCODE, left, right));
break;
case LS:
oneShortOp(getOpcodeGroup1(CMPHS_OPCODE, left, right));
break;
case LE:
oneShortOp(getOpcodeGroup1(CMPGE_OPCODE, left, right));
break;
case LT:
oneShortOp(getOpcodeGroup1(CMPGT_OPCODE, left, right));
break;
default:
ASSERT_NOT_REACHED();
}
}
void cmppl(RegisterID reg)
{
uint16_t opc = getOpcodeGroup2(CMPPL_OPCODE, reg);
oneShortOp(opc);
}
void cmppz(RegisterID reg)
{
uint16_t opc = getOpcodeGroup2(CMPPZ_OPCODE, reg);
oneShortOp(opc);
}
void cmpEqImmR0(int imm, RegisterID dst)
{
uint16_t opc = getOpcodeGroup5(CMPEQIMM_OPCODE, imm);
oneShortOp(opc);
}
void testlRegReg(RegisterID src, RegisterID dst)
{
uint16_t opc = getOpcodeGroup1(TST_OPCODE, dst, src);
oneShortOp(opc);
}
void testlImm8r(int imm, RegisterID dst)
{
ASSERT((dst == SH4Registers::r0) && (imm <= 255) && (imm >= 0));
uint16_t opc = getOpcodeGroup5(TSTIMM_OPCODE, imm);
oneShortOp(opc);
}
void nop()
{
oneShortOp(NOP_OPCODE, false);
}
void sett()
{
oneShortOp(SETT_OPCODE);
}
void clrt()
{
oneShortOp(CLRT_OPCODE);
}
void fschg()
{
oneShortOp(FSCHG_OPCODE);
}
void bkpt()
{
oneShortOp(BRK_OPCODE, false);
}
void branch(uint16_t opc, int label)
{
switch (opc) {
case BT_OPCODE:
ASSERT((label <= 127) && (label >= -128));
oneShortOp(getOpcodeGroup5(BT_OPCODE, label));
break;
case BRA_OPCODE:
ASSERT((label <= 2047) && (label >= -2048));
oneShortOp(getOpcodeGroup6(BRA_OPCODE, label));
break;
case BF_OPCODE:
ASSERT((label <= 127) && (label >= -128));
oneShortOp(getOpcodeGroup5(BF_OPCODE, label));
break;
default:
ASSERT_NOT_REACHED();
}
}
void branch(uint16_t opc, RegisterID reg)
{
switch (opc) {
case BRAF_OPCODE:
oneShortOp(getOpcodeGroup2(BRAF_OPCODE, reg));
break;
case JMP_OPCODE:
oneShortOp(getOpcodeGroup2(JMP_OPCODE, reg));
break;
case JSR_OPCODE:
oneShortOp(getOpcodeGroup2(JSR_OPCODE, reg));
break;
case BSRF_OPCODE:
oneShortOp(getOpcodeGroup2(BSRF_OPCODE, reg));
break;
default:
ASSERT_NOT_REACHED();
}
}
void ldspr(RegisterID reg)
{
uint16_t opc = getOpcodeGroup2(LDSPR_OPCODE, reg);
oneShortOp(opc);
}
void stspr(RegisterID reg)
{
uint16_t opc = getOpcodeGroup2(STSPR_OPCODE, reg);
oneShortOp(opc);
}
void extub(RegisterID src, RegisterID dst)
{
uint16_t opc = getOpcodeGroup1(EXTUB_OPCODE, dst, src);
oneShortOp(opc);
}
void extuw(RegisterID src, RegisterID dst)
{
uint16_t opc = getOpcodeGroup1(EXTUW_OPCODE, dst, src);
oneShortOp(opc);
}
// float operations
void ldsrmfpul(RegisterID src)
{
uint16_t opc = getOpcodeGroup2(LDS_RM_FPUL_OPCODE, src);
oneShortOp(opc);
}
void fneg(FPRegisterID dst)
{
uint16_t opc = getOpcodeGroup2(FNEG_OPCODE, dst);
oneShortOp(opc, true, false);
}
void fsqrt(FPRegisterID dst)
{
uint16_t opc = getOpcodeGroup2(FSQRT_OPCODE, dst);
oneShortOp(opc, true, false);
}
void stsfpulReg(RegisterID src)
{
uint16_t opc = getOpcodeGroup2(STS_FPUL_RN_OPCODE, src);
oneShortOp(opc);
}
void floatfpulfrn(RegisterID src)
{
uint16_t opc = getOpcodeGroup2(FLOAT_OPCODE, src);
oneShortOp(opc, true, false);
}
void fmull(FPRegisterID src, FPRegisterID dst)
{
uint16_t opc = getOpcodeGroup1(FMUL_OPCODE, dst, src);
oneShortOp(opc, true, false);
}
void fmovsReadrm(RegisterID src, FPRegisterID dst)
{
uint16_t opc = getOpcodeGroup1(FMOVS_READ_RM_OPCODE, dst, src);
oneShortOp(opc, true, false);
}
void fmovsWriterm(FPRegisterID src, RegisterID dst)
{
uint16_t opc = getOpcodeGroup1(FMOVS_WRITE_RN_OPCODE, dst, src);
oneShortOp(opc, true, false);
}
void fmovsWriter0r(FPRegisterID src, RegisterID dst)
{
uint16_t opc = getOpcodeGroup1(FMOVS_WRITE_R0RN_OPCODE, dst, src);
oneShortOp(opc, true, false);
}
void fmovsReadr0r(RegisterID src, FPRegisterID dst)
{
uint16_t opc = getOpcodeGroup1(FMOVS_READ_R0RM_OPCODE, dst, src);
oneShortOp(opc, true, false);
}
void fmovsReadrminc(RegisterID src, FPRegisterID dst)
{
uint16_t opc = getOpcodeGroup1(FMOVS_READ_RM_INC_OPCODE, dst, src);
oneShortOp(opc, true, false);
}
void fmovsWriterndec(FPRegisterID src, RegisterID dst)
{
uint16_t opc = getOpcodeGroup1(FMOVS_WRITE_RN_DEC_OPCODE, dst, src);
oneShortOp(opc, true, false);
}
void ftrcRegfpul(FPRegisterID src)
{
uint16_t opc = getOpcodeGroup2(FTRC_OPCODE, src);
oneShortOp(opc, true, false);
}
void fldsfpul(RegisterID src)
{
uint16_t opc = getOpcodeGroup2(FLDS_FRM_FPUL_OPCODE, src);
oneShortOp(opc);
}
void fstsfpul(RegisterID src)
{
uint16_t opc = getOpcodeGroup2(FSTS_FPUL_FRN_OPCODE, src);
oneShortOp(opc);
}
void ldsfpscr(RegisterID reg)
{
uint16_t opc = getOpcodeGroup2(LDSFPSCR_OPCODE, reg);
oneShortOp(opc);
}
void stsfpscr(RegisterID reg)
{
uint16_t opc = getOpcodeGroup2(STSFPSCR_OPCODE, reg);
oneShortOp(opc);
}
// double operations
void dcnvds(FPRegisterID src)
{
uint16_t opc = getOpcodeGroup7(FCNVDS_DRM_FPUL_OPCODE, src >> 1);
oneShortOp(opc);
}
void dcmppeq(FPRegisterID src, FPRegisterID dst)
{
uint16_t opc = getOpcodeGroup8(FCMPEQ_OPCODE, dst >> 1, src >> 1);
oneShortOp(opc);
}
void dcmppgt(FPRegisterID src, FPRegisterID dst)
{
uint16_t opc = getOpcodeGroup8(FCMPGT_OPCODE, dst >> 1, src >> 1);
oneShortOp(opc);
}
void dmulRegReg(FPRegisterID src, FPRegisterID dst)
{
uint16_t opc = getOpcodeGroup8(FMUL_OPCODE, dst >> 1, src >> 1);
oneShortOp(opc);
}
void dsubRegReg(FPRegisterID src, FPRegisterID dst)
{
uint16_t opc = getOpcodeGroup8(FSUB_OPCODE, dst >> 1, src >> 1);
oneShortOp(opc);
}
void daddRegReg(FPRegisterID src, FPRegisterID dst)
{
uint16_t opc = getOpcodeGroup8(FADD_OPCODE, dst >> 1, src >> 1);
oneShortOp(opc);
}
void dmovRegReg(FPRegisterID src, FPRegisterID dst)
{
uint16_t opc = getOpcodeGroup8(FMOV_OPCODE, dst >> 1, src >> 1);
oneShortOp(opc);
}
void ddivRegReg(FPRegisterID src, FPRegisterID dst)
{
uint16_t opc = getOpcodeGroup8(FDIV_OPCODE, dst >> 1, src >> 1);
oneShortOp(opc);
}
void dsqrt(FPRegisterID dst)
{
uint16_t opc = getOpcodeGroup7(FSQRT_OPCODE, dst >> 1);
oneShortOp(opc);
}
void dneg(FPRegisterID dst)
{
uint16_t opc = getOpcodeGroup7(FNEG_OPCODE, dst >> 1);
oneShortOp(opc);
}
void fmovReadrm(RegisterID src, FPRegisterID dst)
{
uint16_t opc = getOpcodeGroup10(FMOVS_READ_RM_OPCODE, dst >> 1, src);
oneShortOp(opc);
}
void fmovWriterm(FPRegisterID src, RegisterID dst)
{
uint16_t opc = getOpcodeGroup9(FMOVS_WRITE_RN_OPCODE, dst, src >> 1);
oneShortOp(opc);
}
void fmovWriter0r(FPRegisterID src, RegisterID dst)
{
uint16_t opc = getOpcodeGroup9(FMOVS_WRITE_R0RN_OPCODE, dst, src >> 1);
oneShortOp(opc);
}
void fmovReadr0r(RegisterID src, FPRegisterID dst)
{
uint16_t opc = getOpcodeGroup10(FMOVS_READ_R0RM_OPCODE, dst >> 1, src);
oneShortOp(opc);
}
void fmovReadrminc(RegisterID src, FPRegisterID dst)
{
uint16_t opc = getOpcodeGroup10(FMOVS_READ_RM_INC_OPCODE, dst >> 1, src);
oneShortOp(opc);
}
void fmovWriterndec(FPRegisterID src, RegisterID dst)
{
uint16_t opc = getOpcodeGroup9(FMOVS_WRITE_RN_DEC_OPCODE, dst, src >> 1);
oneShortOp(opc);
}
void floatfpulDreg(FPRegisterID src)
{
uint16_t opc = getOpcodeGroup7(FLOAT_OPCODE, src >> 1);
oneShortOp(opc);
}
void ftrcdrmfpul(FPRegisterID src)
{
uint16_t opc = getOpcodeGroup7(FTRC_OPCODE, src >> 1);
oneShortOp(opc);
}
// Various move ops
void movImm8(int imm8, RegisterID dst)
{
ASSERT((imm8 <= 127) && (imm8 >= -128));
uint16_t opc = getOpcodeGroup3(MOVIMM_OPCODE, dst, imm8);