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Forked from lowRISC/ibex
Ibex is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, previously known as zero-riscy.
SystemVerilog
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Forked from openhwgroup/core-v-verif
Functional verification project for the CORE-V family of RISC-V cores.
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105 contributions in the last year
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June 2021
Created 3 commits in 2 repositories
Created 1 repository
- dawidzim/cv32e40x SystemVerilog
Created a pull request in lowRISC/ibex that received 12 comments
Changes simulation command for Riviera 2021.04
Hey! Few changes in Riviera-PRO compilation and simulation command
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Opened 2 other pull requests in 2 repositories
openhwgroup/cv32e40x
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merged
lowRISC/ibex
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merged
Created an issue in openhwgroup/core-v-verif that received 1 comment
Assign to member of enum in cv32e40p mm_ram.sv
Bug name
Assign to member of enum in https://github.com/openhwgroup/core-v-verif/blob/master/cv32e40p/tb/core/mm_ram.sv
Type
Compile error (hopefu…
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comment

