The Wayback Machine - https://web.archive.org/web/20210618182400/https://github.com/dawidzim
Skip to content
Avatar

Achievements

Achievements

Block or Report

Block or report dawidzim

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse

Popular repositories

  1. Forked from olofk/edalize

    An abstraction library for interfacing EDA tools

    Python

  2. Forked from lowRISC/ibex

    Ibex is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, previously known as zero-riscy.

    SystemVerilog

  3. Forked from olofk/axi_node

    SystemVerilog

  4. Forked from chipsalliance/Cores-SweRV

    SweRV EH1 core

    SystemVerilog

  5. Forked from chipsalliance/Cores-SweRVolf

    FuseSoC-based SoC for SweRV EH1

    Coq

  6. Forked from openhwgroup/core-v-verif

    Functional verification project for the CORE-V family of RISC-V cores.

    Assembly

105 contributions in the last year

Jun Jul Aug Sep Oct Nov Dec Jan Feb Mar Apr May Jun Mon Wed Fri

Contribution activity

June 2021

Created 3 commits in 2 repositories
Created 1 repository

Created a pull request in lowRISC/ibex that received 12 comments

Changes simulation command for Riviera 2021.04

Hey! Few changes in Riviera-PRO compilation and simulation command

+2 −4 12 comments
Opened 2 other pull requests in 2 repositories
openhwgroup/cv32e40x
1 merged
lowRISC/ibex
1 merged

Created an issue in openhwgroup/core-v-verif that received 1 comment

Assign to member of enum in cv32e40p mm_ram.sv

Bug name Assign to member of enum in https://github.com/openhwgroup/core-v-verif/blob/master/cv32e40p/tb/core/mm_ram.sv Type Compile error (hopefu…

1 comment
Opened 1 other issue in 1 repository
openhwgroup/cv32e40x
1 open

Seeing something unexpected? Take a look at the GitHub profile guide.