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readme.md

PyOCD-RISCV32

Generating with a pythonscript JTAG-sequences for the debug port of different RISCV32 cores:

using the API of pyftdi.

To try it in simulation verilator is needed. For pulp do the following: Build the firmware pulp.bin: python3 mkfw.py pulp floathw rvf

Build the simulation: cd pulp make all Run the simulation: output_verilator/riscv_soc or with tracing enabled: output_verilator/riscv_soc vcd Finally run dbgjtag.py: python3 dbgjtag.py s pulp

To use it on real hardware (with an ARM-USB-TINY-H): python3 dbgjtag.py f pulp

with an USB-Blaster and virtual JTAG: python3 dbgjtag.py v murax

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Python script for controlling the debug-jtag port of riscv cores

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