RISC-V Hardware Leftovers
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WARP-V: A RISC-V CPU Core Generator Supporting MIPS ISA - CNX Software
If you have been working on open standard RISC-V ISA CPU cores, there is a high chance that you have come across WARP-V. For newbies, WARP-V is a RISC-V CPU core generator written in TL-Verilog (Transaction-Level Verilog) that supports not only RISC-V but also MIPS ISA. WARP-V has been in discussion for a while due to its unparalleled architectural scalability in a small amount of code.
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Russia's Elbrus has a RISC-V competitor as Yadro prepares native chips for launch
Russia's Yadro and subsidiary Syntacore have announced an effort to develop homegrown processors based on the free and open RISC-V architecture.
A report in local newspaper Ведомости, first spotted in the west by AnandTech, pointed to state-owned Rostec providing up to 30bn rubles (around $400m, £290m) in backing to Yadro and Syntacore to build a range of devices featuring RISC-V chips.
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Compsci eggheads bring OpenCL framework to RISC-V to push parallel performance
A quartet of computer science boffins have showcased work on bringing the OpenCL programming framework to a wide range of RISC-V chips – improving their suitability for highly parallel workloads in science and beyond.
Born at the University of California at Berkeley in 2010, following an earlier research project from the 1980s dubbed Berkeley RISC, which would eventually become the SPARC architecture, RISC-V is both free and open source. As a result, anyone can build chips implementing the RISC-V architecture and can modify and expand it at will, adding new features or tweaking existing ones as required.
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