Skip to content

Commit 2548ea2

Browse files
mmlrmmlr
committed
* Add the framework for adding an arch specific module to the PCI bus_manager.
* Implement such a module for x86 which currently exports only an MSI API. * Implement the PCI part for configuring and enabling MSIs. * Some automatic whitespace cleanup. git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@36223 a95241bf-73f2-0310-859d-f6bbb57e9c96
1 parent bafcab9 commit 2548ea2

File tree

12 files changed

+493
-19
lines changed

12 files changed

+493
-19
lines changed

‎headers/os/drivers/PCI.h

Lines changed: 35 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -83,7 +83,7 @@ typedef struct pci_info {
8383
ulong rom_base_pci; /* rom base addr, viewed from pci */
8484
uchar interrupt_line; /* interrupt line */
8585
uchar interrupt_pin; /* interrupt pin */
86-
ushort bridge_control;
86+
ushort bridge_control;
8787
ushort subsystem_id; /* subsystem (add-in card) id */
8888
ushort subsystem_vendor_id; /* subsystem (add-in card) vendor id */
8989
} h1;
@@ -109,7 +109,7 @@ typedef struct pci_info {
109109
ushort secondary_status;
110110
ushort bridge_control;
111111
#endif /* __HAIKU_PCI_BUS_MANAGER_TESTING */
112-
} h2;
112+
} h2;
113113
} u;
114114
} pci_info;
115115

@@ -221,7 +221,7 @@ struct pci_module_info {
221221
#define PCI_primary_bus 0x18 /* (1 byte) */
222222
#define PCI_secondary_bus 0x19 /* (1 byte) */
223223
#define PCI_subordinate_bus 0x1A /* (1 byte) */
224-
#define PCI_secondary_latency 0x1B /* (1 byte) latency of secondary bus */
224+
#define PCI_secondary_latency 0x1B /* (1 byte) latency of secondary bus */
225225
#define PCI_io_base 0x1C /* (1 byte) io base address register for 2ndry bus*/
226226
#define PCI_io_limit 0x1D /* (1 byte) */
227227
#define PCI_secondary_status 0x1E /* (2 bytes) */
@@ -236,7 +236,7 @@ struct pci_module_info {
236236
#define PCI_sub_vendor_id_1 0x34 /* (2 bytes) */
237237
#define PCI_sub_device_id_1 0x36 /* (2 bytes) */
238238
#define PCI_bridge_rom_base 0x38
239-
#define PCI_bridge_control 0x3E /* (2 bytes) */
239+
#define PCI_bridge_control 0x3E /* (2 bytes) */
240240

241241

242242
/* PCI type 2 header offsets */
@@ -245,7 +245,7 @@ struct pci_module_info {
245245
#define PCI_primary_bus_2 0x18 /* (1 byte) */
246246
#define PCI_secondary_bus_2 0x19 /* (1 byte) */
247247
#define PCI_subordinate_bus_2 0x1A /* (1 byte) */
248-
#define PCI_secondary_latency_2 0x1B /* (1 byte) latency of secondary bus */
248+
#define PCI_secondary_latency_2 0x1B /* (1 byte) latency of secondary bus */
249249
#define PCI_memory_base0_2 0x1C /* (4 bytes) */
250250
#define PCI_memory_limit0_2 0x20 /* (4 bytes) */
251251
#define PCI_memory_base1_2 0x24 /* (4 bytes) */
@@ -588,8 +588,8 @@ struct pci_module_info {
588588

589589
/** types of PCI header */
590590

591-
#define PCI_header_type_generic 0x00
592-
#define PCI_header_type_PCI_to_PCI_bridge 0x01
591+
#define PCI_header_type_generic 0x00
592+
#define PCI_header_type_PCI_to_PCI_bridge 0x01
593593
#define PCI_header_type_cardbus 0x02
594594

595595

@@ -677,6 +677,34 @@ struct pci_module_info {
677677
#define PCI_pm_state_d2 0x02
678678
#define PCI_pm_state_d3 0x03
679679

680+
/** MSI registers **/
681+
#define PCI_msi_control 0x02
682+
#define PCI_msi_address 0x04
683+
#define PCI_msi_address_high 0x08
684+
#define PCI_msi_data 0x08
685+
#define PCI_msi_data_64bit 0x0c
686+
#define PCI_msi_mask 0x10
687+
#define PCI_msi_pending 0x14
688+
689+
/** MSI control register values **/
690+
#define PCI_msi_control_enable 0x0001
691+
#define PCI_msi_control_vector 0x0100
692+
#define PCI_msi_control_64bit 0x0080
693+
#define PCI_msi_control_mme_mask 0x0070
694+
#define PCI_msi_control_mme_1 0x0000
695+
#define PCI_msi_control_mme_2 0x0010
696+
#define PCI_msi_control_mme_4 0x0020
697+
#define PCI_msi_control_mme_8 0x0030
698+
#define PCI_msi_control_mme_16 0x0040
699+
#define PCI_msi_control_mme_32 0x0050
700+
#define PCI_msi_control_mmc_mask 0x000e
701+
#define PCI_msi_control_mmc_1 0x0000
702+
#define PCI_msi_control_mmc_2 0x0002
703+
#define PCI_msi_control_mmc_4 0x0004
704+
#define PCI_msi_control_mmc_8 0x0006
705+
#define PCI_msi_control_mmc_16 0x0008
706+
#define PCI_msi_control_mmc_32 0x000a
707+
680708
#ifdef __cplusplus
681709
}
682710
#endif

‎headers/os/drivers/PCI_x86.h

Lines changed: 38 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,38 @@
1+
#ifndef PCI_X86_H
2+
#define PCI_X86_H
3+
4+
#include <SupportDefs.h>
5+
#include <module.h>
6+
7+
typedef struct pci_x86_module_info {
8+
module_info info;
9+
10+
uint8 (*get_msi_count)(
11+
uint8 bus, /* bus number */
12+
uint8 device, /* device # on bus */
13+
uint8 function); /* function # in device */
14+
15+
status_t (*configure_msi)(
16+
uint8 bus, /* bus number */
17+
uint8 device, /* device # on bus */
18+
uint8 function, /* function # in device */
19+
uint8 count, /* count of vectors desired */
20+
uint8 *startVector); /* first configured vector */
21+
status_t (*unconfigure_msi)(
22+
uint8 bus, /* bus number */
23+
uint8 device, /* device # on bus */
24+
uint8 function); /* function # in device */
25+
26+
status_t (*enable_msi)(
27+
uint8 bus, /* bus number */
28+
uint8 device, /* device # on bus */
29+
uint8 function); /* function # in device */
30+
status_t (*disable_msi)(
31+
uint8 bus, /* bus number */
32+
uint8 device, /* device # on bus */
33+
uint8 function); /* function # in device */
34+
} pci_x86_module_info;
35+
36+
#define B_PCI_X86_MODULE_NAME "bus_managers/pci/x86/v1"
37+
38+
#endif // PCI_X86_H

‎src/add-ons/kernel/bus_managers/pci/Jamfile

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3,12 +3,13 @@ SubDir HAIKU_TOP src add-ons kernel bus_managers pci ;
33
UsePrivateKernelHeaders ;
44
UsePrivateHeaders shared ;
55
UsePrivateHeaders [ FDirName kernel util ] ;
6+
UseHeaders [ FDirName $(SUBDIR) arch $(TARGET_ARCH) ] ;
67

78
KernelAddon pci :
89
pci.cpp
910
pci_fixup.cpp
1011
pci_info.cpp
11-
pci_module.c
12+
pci_module.cpp
1213
pci_root.cpp
1314
pci_device.cpp
1415
: pci_arch_bus_manager.a

‎src/add-ons/kernel/bus_managers/pci/arch/x86/Jamfile

Lines changed: 5 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -2,12 +2,14 @@ SubDir HAIKU_TOP src add-ons kernel bus_managers pci arch x86 ;
22

33
SubDirHdrs [ FDirName $(SUBDIR) $(DOTDOT) $(DOTDOT) ] ;
44

5-
UsePrivateHeaders kernel [ FDirName kernel arch x86 ] ;
5+
UsePrivateHeaders kernel [ FDirName kernel arch x86 ] [ FDirName kernel util ] ;
66

7-
KernelStaticLibrary pci_arch_bus_manager :
7+
KernelStaticLibrary pci_arch_bus_manager :
8+
pci_arch_info.cpp
9+
pci_arch_module.cpp
810
pci_bios.c
911
pci_controller.c
1012
pci_io.c
1113
pci_irq.c
14+
pci_msi.cpp
1215
;
13-

‎src/add-ons/kernel/bus_managers/pci/arch/x86/pci_arch_info.cpp

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,7 @@
1+
#include "pci_arch_info.h"
2+
3+
void
4+
pci_read_arch_info(PCIDev *dev)
5+
{
6+
pci_read_msi_info(dev);
7+
}

‎src/add-ons/kernel/bus_managers/pci/arch/x86/pci_arch_info.h

Lines changed: 13 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,13 @@
1+
#ifndef _PCI_ARCH_INFO_H
2+
#define _PCI_ARCH_INFO_H
3+
4+
#include "pci_msi.h"
5+
6+
typedef struct pci_arch_info {
7+
msi_info msi;
8+
} pci_arch_info;
9+
10+
11+
void pci_read_arch_info(PCIDev *device);
12+
13+
#endif // _PCI_ARCH_INFO_H

‎src/add-ons/kernel/bus_managers/pci/arch/x86/pci_arch_module.cpp

Lines changed: 30 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,30 @@
1+
#include <PCI_x86.h>
2+
#include "pci_msi.h"
3+
4+
5+
static int32
6+
pci_arch_module_std_ops(int32 op, ...)
7+
{
8+
switch (op) {
9+
case B_MODULE_INIT:
10+
case B_MODULE_UNINIT:
11+
return B_OK;
12+
}
13+
14+
return B_BAD_VALUE;
15+
}
16+
17+
18+
pci_x86_module_info gPCIArchModule = {
19+
{
20+
B_PCI_X86_MODULE_NAME,
21+
0,
22+
pci_arch_module_std_ops
23+
},
24+
25+
&pci_get_msi_count,
26+
&pci_configure_msi,
27+
&pci_unconfigure_msi,
28+
&pci_enable_msi,
29+
&pci_disable_msi
30+
};

0 commit comments

Comments
 (0)