EDN Flashback: Self-contained TV receiver uses 24 transistors

Circuit diagram of complete receiver

Editor's note: Click here for a schematic�(PDF, 1.2 Mbytes)�.

Triode transistor tuner must be operated with low side injection of oscillator frequency on high channels because of cutoff frequency of 2N623 diffused-base transistors. In alternate tetrode tuner, high side injection can be employed on all channels. Oscillator in triode tuner must provide 300 �watts to mixer; in tetrode tuner, only 40 to 60 �watts needed. Due to use of triode tuner, video IF response curve made symmetrical. 45.25 mc point is 5 db down from top while 41.25 mc is 20-22 db down. Without traps, adjacent channel sound and video rejection down about same extent as 41.25 mc. Capacitive neutralization is employed on all video IF stages. In first two stages, the 3.9 MMF capacitors are selected for minimum forward transmission of signal at maximum AGC. Remaining neutralizing capacitors are chosen for maximum neutralization. In the last video IF stage, two 50 MF capacitors serve to maintain the operating point of stage at modulation peaks because this stage does not operate strictly class A. Most of the circuit is not critical with respect to transistor replacement.

However, it is probable that replacement of 4th IF transistor would require readjustment of double tuned coupling circuit.

In the video detector, a small d-c bias voltage is applied to the cathode of the IN295 to maintain rectifying linearity at low signal levels. Maximum video signal made available to first video amplifier from detector is 3v P-P. However, maximum voltage fed to 9QP4 cathode if 40v P-P, limited by 48 volt d-c potential of output video amplifier. Maximum voltage gain of video amplifier section is 40 with a 3-mc passband. Contrast is controlled by 2,500-ohm potentiometer in emitter circuit of 2nd video amplifier in accordance with conventional practice.

The sound system is straightforward, with two 4.5-mc IF amplifiers, one of which serves as a reflex audio amplifier, a ratio detector, a 2N185 driver and a push-pull, class-B audio output stage. A series resonant 4.5-mc circuit links the emitter of the first video amplifier with the first sound IF stage. Input impedance of the sound amplifier is 300 ohms and the series resonant circuit enables this to match the emitter circuit impedance of the video amplifier. D5 serves as an AM limiter by clipping negative segment of signal at collector of 1st sound IF. Tuned circuit then acts to smooth out the positive half of signal to same level.

Sync pulse positive signal is applied to X11 from the first video amplifier. 0.7 volt P-P will drive this transistor from cutoff to saturation. X12 then serves as a sync amplifier for vertical pulses and an emitter follower for the horizontal deflection system. For the vertical pulses, the 1,000-ohm resistor and 0.1 MF capacitor between X12 and X13 provide the major portion of integration with additional integration occurring in the emitter of X13.

The vertical deflection system requires only two stages, a blocking oscillator and an alloy junction vertical output amplifier. The sawtooth deflection wave is developed across C1 and C2 in series, and then passed on to X15. C2 is also part of a feedback network from the emitter of X15 to improve the linearity of the deflection waveform. Separate vertical linearity and vertical size controls are available, but being part of the same network, tend to be interdependent in adjustment, together with the bias control. The latter potentiometer sets the operating current for the vertical output amplifier.

In the horizontal system, negative-going sync pulses from X12 are compared with a sawtooth wave developed from voltage pulses obtained from the output circuit of X24. The resulting d-c potential is then passed through a long time-constant filter, (.01 and .02 MF capacitors and 2.2K resistor) and anti-hunt network (1.5K resistor and 5 MF capacitor) to a blocking oscillator through a d-c amplifier. The driving signal fed to X23 is a square wave pulse. However, due to the inductive coupling, the a-c axis of this pulse provides enough forward bias to drive the transistor to saturation during conduction, while the positive-going pulse sharply cuts X23 off during retrace. A similar situation exists in the input circuit of X24, with a variable 50-ohm potentiometer in the base circuit to limit the d-c power consumption of the transistor.

The peak voltage developed across T6 during beam retrace is kept at about 80v by adjusting the self-resonant frequency of the secondary of this high-voltage transformer to approximately 100 kc. Without this adjustment, the voltage peak would rise to 110v and place an extra burden on transistor selection. Peak emitter current in X24 just prior to start of retrace is two amps.