verilog

Here are 1,508 public repositories matching this topic...

platformio / platformio-core

PlatformIO is a professional collaborative platform for embedded development 👽 A place where Developers and Teams have true Freedom! No more vendor lock-in!

Updated Jul 15, 2020
Python

freechipsproject / chisel3

Star

Chisel 3: A Modern Hardware Design Language

scala chip-generator chisel rtl chisel3 firrtl verilog

Updated Jul 20, 2020
Scala

SI-RISCV / e200_opensource

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The Ultra-Low Power RISC Core

cpu core verilog china risc-v ultra-low-power

Updated Jan 2, 2020
Verilog

jbush001 / NyuziProcessor

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GPGPU microprocessor architecture

processor-architecture fpga hardware gpu graphics verilog microprocessor gpu-computing

Updated Apr 19, 2020
C

clash-lang / clash-compiler

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Haskell to VHDL/Verilog/SystemVerilog compiler

haskell asic fpga vhdl verilog systemverilog hardware-description-language

Updated Jul 21, 2020
Haskell

darklife / darkriscv

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opensouce RISC-V implemented from scratch in one night!

fpga riscv rtl verilog risc-v rv32i softcore processor-design rv32e

Updated Jul 21, 2020
Verilog

SpinalHDL / VexRiscv

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A FPGA friendly 32 bit RISC-V CPU implementation

cpu fpga vhdl riscv verilog soc spinalhdl softcore

Updated Jul 16, 2020
Assembly

open-sdr / openwifi

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open-source IEEE802.11/Wi-Fi baseband chip/FPGA design

linux fpga zynq hls wifi verilog xilinx sdr analog-devices ieee80211 dma software-defined-radio ofdm csma ad9361 802-11 mac80211 openwifi

Updated Jul 4, 2020
C

FPGAwars / icestudio

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❄️ Visual editor for open FPGA boards

javascript editor fpga ide blocks verilog icestorm lattice icestudio

Updated Jun 25, 2020
JavaScript

ZipCPU / zipcpu

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A small, light weight, RISC CPU soft core

cpu fpga verilog cross-compiler wishbone soft-core verilator zipcpu wishbone-bus risc-cpu

Updated Jul 16, 2020
Verilog

analogdevicesinc / hdl

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HDL libraries and projects

fpga verilog hdl analog-devices jesd204b

Updated Jul 21, 2020
Verilog

cocotb / cocotb

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cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python

python test vhdl verification verilog uvm

Updated Jul 21, 2020
Python

SpinalHDL / SpinalHDL

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SpinalHDL core

scala fpga vhdl rtl verilog

Updated Jul 20, 2020
Scala

platformio / platformio-vscode-ide

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PlatformIO IDE for VSCode: The next generation integrated development environment for IoT

debugger iot microcontroller embedded fpga hardware vscode platformio verilog

Updated Jun 15, 2020
JavaScript

platformio / platformio-atom-ide

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PlatformIO IDE for Atom: The next generation integrated development environment for IoT

atom debugger iot arduino esp8266 build microcontroller embedded fpga libraries hardware esp32 ide mbed platformio verilog lattice

Updated Jun 16, 2020
JavaScript

vmware / cascade

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A Just-In-Time Compiler for Verilog from VMware Research

fpga hardware repl jit verilog just-in-time

Updated Apr 15, 2020
C++

Obijuan / open-fpga-verilog-tutorial

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Learn how to design digital systems and synthesize them into an FPGA using only opensource tools

linux fpga verilog icestorm lattice fpgawars openfpga

Updated Apr 15, 2020
Verilog

verilog-to-routing / vtr-verilog-to-routing

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Verilog to Routing -- Open Source CAD Flow for FPGA Research

fpga routing eda cad verilog synthesis placement vtr vpr

Updated Jul 21, 2020
C++

verilator / verilator

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Verilator open-source SystemVerilog simulator and lint system

cpp verilog compilers systemc system-verilog verilator verilog-simulator

Updated Jul 20, 2020
C++

syntacore / scr1

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SCR1 is a high-quality open-source RISC-V MCU core in Verilog

core riscv rtl ip verilog risc-v rv32i rv32e rv32imc rv32emc

Updated Jul 16, 2020
SystemVerilog

openrisc / mor1kx

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mor1kx - an OpenRISC 1000 processor IP core

verilog openrisc

Updated Apr 17, 2020
Verilog

FPGAwars / apio

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🌱 Open source ecosystem for open FPGA boards

python cli package fpga manager verilog icestorm lattice apio

Updated May 12, 2020
Python

drom / awesome-hdl

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Hardware Description Languages

awesome vhdl verilog awesome-list hdl hardware-description-language

Updated May 25, 2020

tommythorn / Reduceron

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FPGA Haskell machine with game changing performance. Reduceron is Matthew Naylor, Colin Runciman and Jason Reich's high performance FPGA softcore for running lazy functional programs, including hardware garbage collection. Reduceron has been implemented on various FPGAs with clock frequency ranging from 60 to 150 MHz depending on the FPGA. A high degree of parallelism allows Reduceron to implement graph evaluation very efficiently. This fork aims to continue development on this, with a view to practical applications. Comments, questions, etc are welcome.

haskell fpga compiler verilog lava