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opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
Updated
May 25, 2022
Verilog
SCR1 is a high-quality open-source RISC-V MCU core in Verilog
Updated
Apr 22, 2022
SystemVerilog
FEWcore é um core RISC-V que segue as especificações RV32E com algumas leves modificações. Este projeto é o trabalho prático da disciplina Organizações de Computadores 2 no semestre 2018/2 da UFMG.
Updated
Dec 15, 2018
Verilog
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